1. Field of the Invention
The present invention generally relates to a row decoder for a semiconductor memory device. More particularly, it relates to a row decoder for a semiconductor memory device in which a pair of pull-up signals among pull-up/pull-down signals, applied to a word line driver, share one pull-down signal, thus driving eight word lines with only the pair of the pull-up signals and the single pull-down signal.
2. Description of the Prior Art
The metal strapping structure or hierarchic word line structure is generally used to drive word lines of a semiconductor memory device.
According to the metal strapping structure, metal lines are arranged on a cell array by word line pitch to be each connected with polysilicon word lines, thereby reducing the resistance of each word line and assuring the high-speed performance. Pitch is the sum of a line width and a line space of each line arranged at regular intervals. In the metal strapping structure, the higher the degree of integration of a memory device becomes, the more the word line pitch is reduced, and failure occurs more frequently in metallization, thus having a disadvantageous yield aspect. Thus, a high-integration memory device such as a 64M dynamic random access memory (DRAM) employs a hierarchic word line structure in which a plurality of hierarchic word line driver circuits are shared for a row decoder's output and divided by a sub-row decoder (pxi generator). Such a hierarchic word line structure may loosen the strict design rule of metallization. FIG. 1 is a circuit diagram of a conventional row decoder for driving a sub-word line. FIG. 2 is a timing diagram of each signal in connection with FIG. 1.
The following description concerns the operation of the conventional row decoder.
A row decoder enable signal (a)xdpd is driven to an active logic state "high" from "low", and row address signals ax23, ax45 and ax67 change their logic states from "low" to "high". If the signal of logic state "high" is transmitted to one node of a transfer gate having a gate to which a power supply voltage Vxg ("Vcc" level), potential signal, and a word line boosting signal pxi(c) is input thereto, bootstrapping occurs so that a value of Vpp, pxi level, is transmitted to the word lines, thus making the word lines active. If a pd node's output, pull-up signal, maintains a logic state "low", and a pu node's output, pull-up signal, goes "low" (precharged state), the pu node's output goes "high" to discharge the word lines.
As described above, the conventional row decoder produces a pair of pull-up and pull-down signals pu&lt;0:3&gt;, pd&lt;0:3&gt;; i.e. pu&lt;0&gt;, pd&lt;0&gt;, pu&lt;1&gt;, pd&lt;1&gt;, pu&lt;2&gt;, pd&lt;2&gt;, pu&lt;3&gt;, and pd&lt;3&gt;, thus actuating memory columns. That is, the conventional row decoder outputs and uses a pair of pull-up and pull-down signals to drive four different word lines. Accordingly, two pairs of pull-up and pull-down signals are needed to drive eight word lines.